FREQUENCY SYNTHESIZERS come in many shapes and sizes. They range from tiny system-on-a-chip (SoC) devices and modules to rugged military-grade rack mount systems and bench-top instruments.1-10

They are also based on a wide array of technologies, from analog to digital in nature, starting with many different signal sources, including voltage-controlled oscillators (VCOs) and surface-acoustic-wave (SAW) resonators. One of the more novel approaches combines both analog and digital techniques: a frequency synthesizer from Synergy Microwave Corp. based on an adaptive mode-coupled-resonator voltage-controlled SAW oscillator (VCSO) circuit. It is part of a frequency synthesizer capable of typical measured phase noise of -152 dBc/Hz offset 10 kHz from a 1-GHz carrier, with less than 6 fs RMS jitter.

A synthesizer using a VCSO within a multiple-loop architecture (model KHPS-50030) was implemented in a module measuring 200 x 120 x 30 mm (Fig. 1). It tunes from 5000 to 5300 MHz in 100-kHz steps and provides output signals at levels to +15 dBm with output flatness of ±3 dB across the tuning range. It settles to a new frequency in 20 ms or less and exhibits harmonic levels of -15 dBc or better and spurious levels of -60 dBc or better. The phase noise is -105 dBc or better offset 1 kHz from the carrier, -115 dBc/Hz or better offset 10 kHz, and -120 dBc/Hz or better offset 100 kHz. It works with an external 10-MHz reference oscillator or, alternately, can be supplied with an internal 10-MHz oven-controlled crystal oscillator (OCXO) reference source. It is designed for a +12-VDC supply and operating temperatures from -10 to +60°C. Designs using this technique of a coupled resonator and adaptive synthesis have already achieved time-domain performance of better than 6 fs and frequency domain performance of 152 dBc/Hz offset 10 kHz from a 1-GHz carrier.

To appreciate these performance levels, it may help to review other available frequency-synthesizer design approaches. One of the most common is the conventional phase-lock-loop (PLL) synthesizer, which consists of a reference phase detector, loop filter, VCO, and VCO divider (N-divider) as shown in Fig. 2. The PLL is typically available as an integrated circuit (IC) with a reference divider, phase detector or phase frequency detector (PFD) with charge pump, and the VCO divider. The relationship between the output frequency fout and reference frequency fref can be described by Eq. 1:

fout = N(fref /R) (1)

The PFD compares the two input signals fref/R and fout/N and produces an error voltage proportional to the phase difference between them. The loop filter attenuates the high-frequency noise components from the PFD output and limits the bandwidth of the error signal. The filtered error voltage is applied to the tuning port of the VCO; the error signal drives the VCO frequency, fout, higher or lower in frequency until the error voltage at the PFD output is zero. Typically, the VCO divider is implemented as a dual-modulus counter to obtain large continuous division of the VCO output. To vary the output frequency fout of the synthesizer, the value of N is changed, and it can be seen from Eq. 1 that the minimum frequency step (called the step size) obtained at the output is given by fref/R. Smaller step size can be obtained by operating the PFD at low frequency—i.e., by increasing the R value (and thus increasing N). The problem with increasing the N value is the noise of the PFD increases. The close in phase noise of the synthesizer is estimated by noise of the synthesizer itself (provided by the manufacturer), PNSYN, and adding 20logN (where N is the N divider value) and 10log(fPFD):

PNTOT = PNSYN + 10logfPRD + 20logN = PNSYN + 10(fREF/R) + 20logN (2)

To minimize phase noise, the value of N should be small. But for fine tuning resolution, the PFD must operate at low frequency, requiring a high value for N and resulting poor phase noise. The conflict eliminates the conventional PLL design for use in low-noise, high-resolution applications. The loop filter in a PLL synthesizer design also limits switching speed. A higher loop bandwidth yields faster switching speed but with excessive noise. A narrow loop bandwidth lowers phase noise but sacrifices switching speed. Obviously, then, the typical phase noise for a conventional PLL synthesizer operating from 500 to 1200 MHz in 500-kHz steps (a model FSW50120-50 from Synergy) includes switching time of less than 5 ms and better than -70 dBc spurious levels with a 10-MHz reference (Fig. 3).

To improve the performance of an integer-based PLL, the N divider can be implemented as a fractional divider, rather than an integer divider. This enables the use of higher PFD frequency and lower N values, thus improving the phase noise. But a fractional-N divider also introduces spurious noise at the output of the synthesizer. In addition to this, even with the fractional N the step-size of the synthesizer cannot go below 1 Hz. Typical fractional-N synthesizer performance from 1600 to 2900 MHz with a 10-MHz reference (a model LFSW160290-50 from Synergy) includes better than 1-ms settling time and spurious levels of -60 dBc or better (Fig. 4).

Multiloop synthesizer architectures with direct-digital synthesizers (DDSs) have been used for tuning resolution better than 1 Hz. Figure 5shows a dual-loop synthesizer where a DDS module combines with a conventional PLL synthesizer. The DDS clock is fed by a selectable frequency synthesizer which provides a fixed set of frequencies based on the parallel select lines. Unfortunately, the DDS approach can generate high spurious output levels. But these spurs can also be predicted and shifted by proper choice of clock frequency. If spurious products fall within the loop bandwidth, by switching the clock frequency, the spurs can be shifted to a band where they can be attenuated. In this dual-loop approach, the output synthesizer�s PFD can be high to improve phase noise while still delivering 1-Hz resolution with a 10-MHz reference. Spurious levels are typically better than -70 dBc from 1100 to 2500 MHz with 1-Hz step size, better than 1-ms switching speed, and low phase noise (Fig. 6).

Synthesizer designers have often relied on multiplying a low-noise crystal oscillator to achieve higher-frequency (1 GHz and higher) output signals. This approach can provide excellent phase noise, but such synthesizers tend to consume a great deal of power, generate high levels of noise, and are large in size. Crystal oscillators at 100 MHz and below are available with phase noise of -160 to -176 dBc/ Hz offset 20 to 100 kHz from a 100-MHz output. When multiplied, the phase noise translates to -140 to -156 dBc/Hz offset 20 to 100 kHz from 1 GHz.

The availability of low-cost, low-noise VCSOs clears the way for small, low-noise synthesizers. Part of using these sources involves modeling the resonators under large signal drive conditions for the better insights about noise dynamics at close-in phase noise, then developing manufacturable methods for producing high-purity oscillators in chip form.4-6

Figure 7shows a typical block diagram for an adaptive mode-coupled VCSO optimized for low noise with vibration, whileFig. 8compares its phase noise at 1 GHz to that of a multiplied crystal oscillator. An adaptive mode-coupled VCSO combined with a digital PFD can be used to form a low-cost, low-power synthesizer module. The digital PFD has a wide capture range, although with high noise floor. An analog PFD has lower noise floor, but narrow capture range. To create a low-noise synthesizer with a wide capture range, a digital PFD can be used in parallel with an analog phase detector. The digital PFD is used for initial acquisition, and the analog detector for final tuning.

Within a DDS architecture, the VCSO can be used to create a synthesizer (Fig. 9) with fast switching speed (about 200 µs). The DDS is used as the feedback divider for high resolution and flexibility in choosing a reference frequency. From 530 to 630 MHz, spurious levels are better than -75 dBc with low phase noise (Fig. 10). Since the analog phase detector has a low noise floor, the synthesizer bandwidth was kept large for fast switching time with low phase noise.

A high-performance synthesizer based on an adaptive modecoupled VCSO and multiple loops, including a sampling PLL, is shown in Fig. 11. The main PLL (Fig. 11b) achieves a coarse lock to the desired output frequency using a 120-MHz reference signal, which can be derived from an internal OCXO or low-noise 800-MHz VCSO. The fine lock is achieved by switching to a fine loop with a reference from PLL1 and fine RF signal from the sampling PLL (Fig. 11c). The sampling PLL features a sampling phase detector with low noise floor. It synthesizes frequencies 120 to 300 MHz away from a desired output frequency by multiplying a reference input signal (from the OCXO or VCSO). Software is used to choose the appropriate reference for best output spurious performance. The fine RF signal is the difference between RF output and the sampling PLL output (generated by mixing the two and filtering the difference). The fine reference to the main PLL is generated from PLL1. The software determines the PLL1 output frequency and appropriate division ratio (M divider) to achieve the desired output frequency. The synthesizer generates 5000 to 5300 MHz in 100-kHz steps with better than -70 dBc spurious and low phase noise (Fig. 12). It has been developed commercially as the model KHPS-50030 mentioned earlier (Fig. 1).

Adaptive mode-coupled VCSOs can also be used in lowspurious synthesizer designs for applications that may require stabilized signals with low levels of spurious noise. In such a frequency synthesizer design, the reference generator multiplies a reference frequency (such as 10 MHz) to 1 GHz through a 1-GHz VCSO-based PLL. This 1-GHz signal is mixed with a signal (20 to 150 MHz) from a DDS or flying- adder-based synthesizer6-10 to produce a reference signal for the main PLL from 1020 to 1150 MHz. The main PLL is basically a loop that translates a low-noise reference to higher frequencies from 4.5 to 11.5 GHz. The programmable divider (divide-by-M or M-divider) can divide by 4, 5, 6, 7, 8, or 9 for frequencies ranging from DC to 15 GHz. The divider output is fed to the translational loop where this signal is mixed with the 1-GHz low-noise reference and fed as a reference to a PLL chip. The reference from the reference generator is applied to the RF port of the PLL chip. A required frequency is obtained at the output by means of proper reference (R) and divider (N) settings.

This last architecture is simple and can be made small. It uses relatively low-cost components. The phase noise is limited by the noise floor of the digital PFD; even though the division ratios are low, the noise floors of the dividers can also degrade the phase-noise performance.